1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a method of forming a self-aligned silicide.
2. Description of the Related Art
As line widths and geometries for semiconductor devices are made smaller, the polysilicon electrodes that form the gates of MOS devices and wiring lines within semiconductor devices become undesirably resistive. Multilayer, electrodes, in which a layer of polysilicon is covered by one or more layers of metals or metal silicides, are used to provide electrodes having a lower resistance than electrodes consisting solely of polysilicon. Silicide electrodes may consist, for example, of a layer of polysilicon having a thickness of approximately 1000-3000.ANG. covered by titanium suicide or another metal silicide to a thickness of greater than 100.ANG.. The silicide layer on the polysilicon layer acts a lower resistance conduction path in parallel with the polysilicon layer over the entire length of the gate electrode. While it has become important to provide a reduced conductivity gate electrode in high-density integrated circuit devices, there have been significant difficulties in implementing this technology in a reliable manner that predictably achieves high levels of performance.
A typical implementation of a multilayer silicide on a polysilicon electrode is the so-called self-aligned silicide ("salicide") structure, aspects of which are illustrated schematically in FIGS. 1A-1C. The illustrated MOS devices are formed on a P-type substrate 100 and include, for example, thick field oxide regions 102 to provide isolation from other, adjacent MOS devices. Conventionally, the device isolation structures may be formed by a local oxidation of silicon (LOCOS) process or one of the modified LOCOS processes. Often, however, device isolation is provided by a shallow trench structure formed by etching a trench into the substrate and refilling the trenches with a deposited insulator, such as chemical vapor deposited (CVD) oxide. A gate oxide layer 103 is formed by thermal oxidation over the active device region between the device isolation structures and a polysilicon gate electrode 104 is formed on the gate oxide layer 103. The polysilicon gate electrode 104 is formed by depositing a layer of undoped polysilicon over the substrate, typically using low pressure chemical vapor deposition (LPCVD), implanting impurities into the polysilicon and annealing to activate the impurities and to render the polysilicon conductive. The polysilicon layer is patterned using conventional photolithography. Polysilicon wiring lines are typically formed elsewhere on the integrated circuit device at the same time and in the same manner as gate electrode 104 is formed.
Doped source/drain regions 106 are formed on either side of the polysilicon gate electrode 104 to define the channel region of the illustrated MOS field effect transistor. Generally, a lightly doped drain (LDD) structure is used in small design rule MOS transistors of the type that are frequently used in modern memory and logic devices. LDD source/drain regions 106 are typically formed in a two step process, beginning with a relatively low level implantation of dopants made self-aligned to polysilicon gate electrode 104 to form the structure illustrated in FIG. 1A. Subsequently, insulating sidewall spacer structure 108 are formed on either side of the gate electrode 104 by first depositing a layer of CVD oxide over the structure described above and then anisotropically etching back the oxide layer to expose the substrate 100 over the lightly doped source/drain regions 106. Etching back the CVD oxide layer produces the spacer oxide structure 108 on either side of the polysilicon gate electrode 104. This process also provides spacer regions along the sides of the polysilicon wiring lines, if the wiring lines are exposed during the oxide deposition and etch back process. After the spacer oxide regions 108 are provided on either side of the polysilicon gate electrode 104, a second, heavier ion implantation is made into the source/drain regions 110, self-aligned to the spacer oxide regions 108.
Referring to FIG. 1B, integrated circuit devices typically include both polysilicon gate electrodes, like gate electrode 104 and polysilicon wiring, lines (not shown) which connect gate electrode to other circuits and which provide other connections in the integrated circuit device. For smaller line widths, even highly doped polysilicon is sufficiently resistant to diminish the performance of MOS and other types of integrated circuits which include polysilicon electrodes or which are connected by polysilicon electrodes due to decreased signal levels and longer RC time constants. To reduce the resistance of conventional polysilicon gate electrodes and wiring lines, further processing of the device described above continues to covert the polysilicon gate electrodes and wiring lines into silicide structures using self-aligned silicide (salicide) techniques. Although a variety of different silicides such as platina silicide and cobalt silicide are known to be acceptable, the silicide most commonly used at this time is titanium silicide, and that structure is described herein. Titanium silicide layers are formed on the polysilicon electrodes and wiring lines and select portions of the substrate, if desired, by first sputtering a layer of titanium over the surface of the device to a thickness of, for example, 200-1000.ANG..
Referring to FIG. 1C, this titanium layer is converted into titanium silicide on the surface of the polysilicon gate electrodes 104 and wiring lines and on the exposed portions of the substrate 100, including the source/drain regions 110, in a two step process. In the first process step, the device is subjected to rapid thermal annealing (RTA) by heating the device to a temperature of up to about 700.degree. C. for about thirty seconds. The first RTA step converts the titanium layer into titanium silicide (nominally TiSi.sub.2) anywhere the titanium layer is in contact with a silicon (crystalline or polycrystalline) surface. The device is then etched using a wet etch consisting of H.sub.2 O.sub.2 and NH.sub.4 OH diluted in water to removed unreacted titanium from the surface of the device and expose the oxide spacers 108 of the device. A layer of titanium silicide 126 is left over the polysilicon gate electrode 104. When the source/drain regions 110 are exposed during the silicidation process, titanium silicide regions 124 are also formed on the surface of the source/drain regions 110. Such titanium silicide regions 124 are often preferred, particularly for logic devices, because silicided source/drain regions provide lower sheet resistance within the source/drain regions 110 and provide better contacts to the source/drain regions 110. Silicide contacts on the source/drain regions 110 are thus preferred so long as the amount of silicon consumed in the silicidation process does not alter the transistor performance or result in excessive junction leakage at the source/drain regions 110.
After the unreacted titanium is etched from the device, further processing is necessary to provide suitable silicide layers on the gate electrode 104 of the device. The first step of the two-step annealing process described to this point forms a relatively high resistivity phase of titanium silicide on the silicon surfaces, so that the illustrated salicide structure does not have as low a resistivity as is desirable. It is accordingly necessary to expose the device to a second step, a second rapid thermal annealing at a temperature in excess of 750.degree. C. for at least ten minutes, to convert the titanium silicide to the lower resistivity phase of titanium silicide. The device is then subjected to further processing to complete fabrication.
The conventional process described above first coverts the titanium deposited on the substrate into titanium silicide with the high resistivity (C49) and then converts the high resistivity of the titanium silicide into the low resistivity (C54) of the titanium silicide by the second annealing step. However, for smaller device geometries, gate electrodes and wiring lines are narrower. Since the polysilicon gate electrodes and the source/drain regions have dopants such as phosphorus or arsenic, producing the titanium silicide in a two-step process is difficult. Furthermore, converting the high resistivity of the titanium silicide into the low resistivity of the titanium silicide becomes more difficult because the high resistivity phase of the titanium silicide has a bigger particle size. On the other hand, since the shallow junction becomes narrower because the substrate is consumed during the process to form the salicide, it makes junction leakage current occur at the PN junction.
For smaller device geometries, gate electrodes and wiring lines are narrower and it becomes increasingly more necessary to reduce the resistivity of gate electrodes and wiring lines within memory and logic devices. On the other hand, it is increasingly more difficult to form appropriate salicide electrode structures for narrower gate electrodes and wiring lines. In particular, it is difficult to provide the low resistivity phase of titanium silicide for narrow line width gate electrodes and wiring lines. It is accordingly desirable to develop better designs and more robust processing techniques for forming low resistance salicide structures.